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STW28NK60Z
N-CHANNEL 600 V - 0.155 - 27A TO-247 Zener-Protected SuperMESHTM MOSFET
Table 1: General Features
TYPE STW28NK60Z
s s s s s s
Figure 1: Package
ID 27 A PW 350 W
VDSS 600 V
RDS(on) < 0.185
TYPICAL RDS(on) = 0.155 EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY TO-247
3 2 1
DESCRIPTION The SuperMESHTM series is obtained through an extreme optimization of ST's well established strip-based PowerMESHTM layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding application. Such series complements ST full range of high vltage MOSFETs including revolutionary MSmeshTM products. APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s IDEAL FOR OFF-LINE POWER SUPPLIES s WELDING MACHINES s LIGHTING
Figure 2: Internal Schematic Diagram
Table 2: Order Codes
PART NUMBER STW28NK60Z MARKING W28NK60Z PACKAGE TO-247 PACKAGING TUBE
Rev. 1 November 2004 1/10
STW28NK60Z
Table 3: Absolute Maximum ratings
Symbol VDS VDGR VGS ID ID IDM(*) PTOT VESD(G-S) dv/dt (1) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 K) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Gate source ESD (HBM-C = 100pF, R = 1.5 K) Peak Diode Recovery voltage slope Storage Temperature Operating Junction Temperature Value 600 600 30 27 17 108 350 2.77 6000 4.5 -55 to 150 Unit V V V A A A W W/C V V/ns C
(*) Pulse width limited by safe operating area (1) ISD 27 A, di/dt 200 A/s, VDD V(BR)DSS, T J TJMAX
Table 4: Thermal Data
Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 0.36 50 300 C/W C/W C
Table 5: Avalanche Characteristics
Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) Max Value 27 500 Unit A mJ
Table 6: Gate-Source Zener Diode
Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Condition Min. 30 Typ. Max Unit A
Igs= 1mA (Open Drain)
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components.
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TABLE 7: ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) On /Off
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 1 mA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125C VGS = 20 V VDS = VGS, ID = 150 A VGS = 10 V, ID = 13.5 A 3 3.75 0.155 Min. 600 1 50 10 4.5 0.185 Typ. Max. Unit S A A A V
Table 8: Dynamic
Symbol gfs (1) Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off-Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDS = 15 V, ID = 13.5 A VDS = 25 V, f = 1 MHz, VGS = 0 Min. Typ. 26 6350 615 125 50 45 135 32 189 34 103 264 Max. Unit S pF pF pF ns ns ns ns nC nC nC
VDD = 300 V, ID = 14 A, RG = 4.7 , VGS = 10 V (Resistive Load see Figure 17)) VDD = 480 V, ID = 28 A, VGS = 10 V
Table 9: Source Drain Diode
Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 27 A, VGS = 0 ISD = 28 A, di/dt = 100 A/s VDD = 35V, Tj = 25C (see test circuit Figure 5) ISD = 28 A, di/dt = 100 A/s VDD = 35V, Tj = 150C (see test circuit Figure 5) 820 10 23.5 1020 14 27.5 Test Conditions Min. Typ. Max. 27 108 1.6 Unit A A V ns C A ns C A
(1) Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (2) Pulse width limited by safe operating area.
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Figure 3: Safe Operating Area Figure 6: Thermal Impedance
Figure 4: Output Characteristics
Figure 7: Transfer Characteristics
Figure 5: Transconductance
Figure 8: Static Drain-source On Resistance
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Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations
Figure 10: Normalized Gate Thereshold Voltage vs Temperature
Figure 13: Normalized On Resistance vs Temperature
Figure 11: Source-Drain Diode Forward Characteristics
Figure 14: Normalized BVDSS vs Temperature
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Figure 15: Maximum Avalanche Energy vs Temperature
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Figure 16: Unclamped Inductive Load Test Circuit Figure 19: Unclamped Inductive Wafeform
Figure 17: Switching Times Test Circuit For Resistive Load
Figure 20: Gate Charge Test Circuit
Figure 18: Test Circuit For Inductive Load Switching and Diode Recovery Times
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TO-247 MECHANICAL DATA
mm. MIN. 4.85 2.20 1.0 2.0 3.0 0.40 19.85 15.45 5.45 14.20 3.70 18.50 3.55 4.50 5.50 3.65 5.50 0.140 0.177 0.216 14.80 4.30 0.560 0.14 0.728 0.143 0.216 TYP MAX. 5.15 2.60 1.40 2.40 3.40 0.80 20.15 15.75 MIN. 0.19 0.086 0.039 0.079 0.118 0.015 0.781 0.608 0.214 0.582 0.17 inch TYP. MAX. 0.20 0.102 0.055 0.094 0.134 0.03 0.793 0.620
DIM. A A1 b b1 b2 c D E e L L1 L2 oP oR S
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Table 10: Revision History
Date 05-Nov-2004 Revision 1 First Release. Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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